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MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs Public

The goal of this proposal is to enhance the research initiatives at the Center for Signal Integrity, Penn State University, Harrisburg (PSH) and advance them to the next level. Signal integrity is defined as the engineering field that analyzes electrical interconnects, such as USB and High-Definition Multimedia Interfaces (HDMI), with the goal of improving the design, reliability and performance of computer systems. Harrisburg, Central Pennsylvania, is known as the Connector Capital of the World, where there are more than twenty-five electrical connector companies that deal with designing and producing interconnects for very high transmission rates. Among them are some of the world's biggest players. The Center for Signal Integrity is focused on the research and development of new signal integrity applications with the goal of helping this local connector industry to remain globally competitive. Note that the impact of the electrical connector industry in Central Pennsylvania's economy is valued over 8 billion dollars. Within the Center, undergraduate and master students have the opportunity to get involved in research and training, and hence have better chances to access internships and employment in local (and national) companies dealing with signal integrity applications. The proposers are targeting to acquire an advanced Bit Error Rate Tester (BERT) and its required accessories that will be used for research and training in support of the local industry. A BERT system is used to verify and characterize high-speed serial data transmission circuits, interfaces (such as USB and HDMIs) and systems. There are several needs for the specialized BERT test equipment requested in this proposal. First, at 10 Gigabits per second (Gb/s), and above, the measurement challenges are stringent. For instance, at that high speed the duration of the bit pulses becomes shorter, indeed below the picosecond range; hence, it becomes extremely difficult to measure jitter. In addition, the instrument intrinsic jitter, at this sub-picosecond range, needs to be taken into account; as a consequence, the measuring equipment's jitter must be significantly less than the jitter to be measured. This piece of equipment will complement the testing capacity that the Center for Signal Integrity possesses. This funding will elevate the Center capabilities to the next level, since it is becoming well-known in the signal integrity community which in turn helps to attract good master students and collaboration interests from other universities and industry. In addition, this proposal will open more opportunities for undergraduate and graduate research and develop courses to train the local workforce in the usage of the equipment. The Center will be also collaborating with the University of South Carolina to provide measuring access to their graduate Signal Integrity program. Furthermore, the requested equipment will be used by the Radio Frequency (RF) Wireless group at PSH. Students at Harrisburg Area Community College and Elizabethtown College will be provided access to learn new measuring skills with a high-end BERT. This project will enhance the partnership with local connector companies to test Field Programmable Gate Arrays (FPGAs) solutions to their research and development teams. The proposers are also integrating research in undergraduate education. For example, Dr. S. Agili and Dr. A. Morales founded the Center for Signal Integrity at PSH, involving undergraduate students, such as rapid prototyping in FPGA, advanced jitter analysis, de-embedding techniques and Monte Carlo simulation for random errors in S-parameters measurements. The proposers are also the PI and Co-PI for an NSF STEM proposal (Award # DUE-1154516) aimed to increase the pool of qualified STEM students, targeted to attract and retain academically-talented and financially needy students of under-represented groups.

This Project Outcomes Report for the General Public is displayed verbatim as submitted by the Principal Investigator (PI) for this award. Any opinions, findings, and conclusions or recommendations expressed in this Report are those of the PI and do not necessarily reflect the views of the National Science Foundation; NSF has not approved or endorsed its content. The main goal of the project is to cement the research initiatives started at the Center for Signal Integrity at Penn State Harrisburg and advance them to the next level. To accomplish this goal, a high speed (32 Gigabits per second) Bit Error Rate Tester (BERT), to verify and characterize high-speed serial data transmission circuits, interfaces and systems, was acquired and installed in the Signal Integrity (SI) Lab at Penn State Harrisburg. This acquisition allows for study and research on PAM 4 implementation, jitter, testing communication channel issues. This piece of equipment complements the testing capacity that the Center for Signal Integrity possesses: Vector Network Analyzer, up to 50 GHz, Two Tektronix Digital Serial Analyzers (up to 20 GHz each), spectrum analyzer, and Altera’s Stratix V boards. After extensive evaluation of competing solutions, the PI/Co-PI decided that Keysight (formerly Agilent) offered the best alternative. The equipment consists of KT-Keysight 32G BERT/PAM4 Measuring System including a JBERT M8020A 32 B, M8195A AWG, 86100D, Infinium DCA-X Oscilloscope and accessories. The equipment was received April 30, 2015 and installed in the SI Lab, room 216, Educational Activities Building (EAB) North. This proposal has opened more opportunities for undergraduate/master teaching and research and to train the local workforce in the usage of the equipment. The BERT equipment is shared with other faculty members within Penn State Harrisburg, private sector partners (through the Center for Signal Integrity), Elizabethtown College, which is a nearby undergraduate college, Harrisburg Area Community College (HACC) and the University of South Carolina. As per the grant, our academic and industrial partners as well as our own students were invited on May 26 and May 27, 2015, to the first round of training provided by Joe Evangelista, a Keysight engineer

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User Aldo W Morales has attached Appendix_D_2017_Annual_Symposium___Penn_State_Harrisburg.pdf to MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has attached Appendix_B_ICCE_2018_KALMAN_FILTER.pdf to MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has attached Appendix_C_implementing-a-SI-course-in-undergraduate-education.pdf to MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has attached /concern/file_sets/8pk02c942x to MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has updated MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has updated MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has updated MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has updated MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs about 2 months ago
User Aldo W Morales has updated MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs 3 months ago
User Aldo W Morales has updated MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs 3 months ago
User Aldo W Morales has attached National_Science_Foundation_MRI_Award_1429941_.docx to MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs 3 months ago
User Aldo W Morales has deposited MRI: Acquisition Bit Error Rate Tester (BERT) to Facilitate Rapid Deployment of High Speed FPGAs 3 months ago